As process technologies scale (or shrink), transistor leakage increases for the same power supply level. Increase in leakage increases power consumption. As market converges to lower power consumption devices, there is a need to reduce power consumption including reducing leakage power of a device.
In current practice, when a logic block goes to sleep (e.g., sleep mode) and all relevant architectural states need to be preserved, it is customary to scan the architectural states out and store them in the cache or another memory. Doing so requires energy and time for reading the architectural states and then writing them back, once the logic block goes back to an active state. This procedure impacts boot-up time and depending on the number of architectural states to be preserved, the wakeup time can be a few hundred to a few thousand cycles. So, if the logic block has to be used after a few tens or hundreds of cycles, it cannot go to a sleep state and have to be kept ‘ON.’ Such strategy increases the overall leakage power during standby.
In another implementation, all the relevant sequentials (latches or flip-flops) are retrofitted with a shadow latch (also called balloon latch), which has higher threshold (Vt) transistor cells than Vt of other transistor cells. Before the logic unit goes to standby (e.g., sleep mode), the data from the sequentials is copied to the shadow latch. The global supply grid (e.g., Vcc grid) of the logic is collapsed while a separate supply line (e.g., Vcc line) routed to the shadow latches is kept alive for state retention. This helps with quick boot-up. However, doing so requires the use and technology support for high Vt cells. Further, a significant number of sequentials need to have shadow cells. In case of external IPs (where we may not have observability into the IP) all the sequentials need to have shadow latches. The term “External IP” generally refers to a hardware block which has been licensed from a third party vendor. Designs for such hardware blocks cannot be modified to build any shadow latch. The area occupied by the shadow latches along with the area to route (and distribute) a separate supply line (e.g., Vcc line) into the logic block, results in a significant overhead.